Question No: 1 ( Marks: 1 ) - Please choose one
The ANSI/IEEE Standard 754 defines a __________Single-Precision Floating Point format for binary numbers. ► 8-bit
► 16-bit
► 32-bit
► 64-bit
Question No: 2 ( Marks: 1 ) - Please choose one
The decimal “17” in BCD will be represented as _________ ► 11101
► 11011
► 10111
► 11110
Question No: 3 ( Marks: 1 ) - Please choose one
The basic building block for a logical circuit is _______ ► A Flip-Flop
► A Logical Gate
► An Adder
► None of given options
Question No: 4 ( Marks: 1 ) - Please choose one
The output of the expression F=A.B.C will be Logic ________ when A=1, B=0, C=1. ADEEL ABBAS ► Undefined
► One
► Zero
► No Output as input is invalid.
Question No: 5 ( Marks: 1 ) - Please choose one
________ is invalid number of cells in a single group formed by the adjacent cells in K-map ► 2
► 8
► 12
► 16
Question No: 6 ( Marks: 1 ) - Please choose one
The PROM consists of a fixed non-programmable ____________ Gate array configured as a decoder. ► AND
► OR
► NOT
► XOR
Question No: 7 ( Marks: 1 ) - Please choose one
___________ is one of the examples of synchronous inputs. ► J-K input
► EN input
► Preset input (PRE)
► Clear Input (CLR)
Question No: 8 ( Marks: 1 ) - Please choose one
___________ is one of the examples of asynchronous inputs. ► J-K input
► S-R input
► D input
► Clear Input (CLR)
Question No: 9 ( Marks: 1 ) - Please choose one
The _____________ input overrides the ________ input ► Asynchronous, synchronous
► Synchronous, asynchronous
► Preset input (PRE), Clear input (CLR)
► Clear input (CLR), Preset input (PRE)
Question No: 10 ( Marks: 1 ) - Please choose one
__________occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. ADEEL ABBAS ► Race condition
► Clock Skew
► Ripple Effect
► None of given options
Question No: 11 ( Marks: 1 ) - Please choose one
Consider an up/down counter that counts between 0 and 15, if external input(X) is “0” the counter counts upward (0000 to 1111) and if external input (X) is “1” the counter counts downward (1111 to 0000), now suppose that the present state is “1100” and X=1, the next state of the counter will be ___________ ► 0000
► 1101
► 1011
► 1111
Question No: 12 ( Marks: 1 ) ADEEL ABBAS - Please choose one
In a state diagram, the transition from a current state to the next state is determined by ► Current state and the inputs
► Current state and outputs
► Previous state and inputs
► Previous state and outputs
Question No: 13 ( Marks: 1 ) - Please choose one
________ is used to minimize the possible no. of states of a circuit. ► State assignment
► State reduction
► Next state table
► State diagram
Question No: 14 ( Marks: 1 ) - Please choose one
________ is used to simplify the circuit that determines the next state. ► State diagram
► Next state table
► State reduction
► State assignment
Question No: 15 ( Marks: 1 ) - Please choose one
The best state assignment tends to ___________. ► Maximizes the number of state variables that don’t change in a group of related states
► Minimizes the number of state variables that don’t change in a group of related states
► Minimize the equivalent states
► None of given options
Question No: 16 ( Marks: 1 ) - Please choose one
The output of this circuit is always ________. 
► 1
► 0
► A
► 
Question No: 17 ( Marks: 1 ) - Please choose one
A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register. ► 1
► 2
► 4
► 8
Question No: 18 ( Marks: 1 ) - Please choose one
5-bit Johnson counter sequences through ____ states ► 7
► 10
► 32
► 25
Question No: 19 ( Marks: 1 ) - Please choose one
Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.) ADEEL ABBAS ► 1100
► 0011
► 0000
► 1111
Question No: 20 ( Marks: 1 ) - Please choose one
The address from which the data is read, is provided by _______ ► Depends on circuitry
► None of given options
► RAM
► Microprocessor
Question No: 21 ( Marks: 1 ) - Please choose one
FIFO is an acronym for __________ ► First In, First Out
► Fly in, Fly Out
► Fast in, Fast Out
► None of given options
Question No: 22 ( Marks: 1 ) - Please choose one
LUT is acronym for _________ ADEEL ABBAS ► Look Up Table
► Local User Terminal
► Least Upper Time Period
► None of given options
Question No: 23 ( Marks: 1 ) - Please choose one
The voltage gain of the Inverting Amplifier is given by the relation ________ ► Vout / Vin = - Rf / Ri
► Vout / Rf = - Vin / Ri
► Rf / Vin = - Ri / Vout
► Rf / Vin = Ri / Vout
Question No: 24 ( Marks: 1 ) - Please choose one
______ of a D/A converter is determined by comparing the actual output of a D/A converter with the expected output. ► Resolution
► Accuracy
► Quantization
► Missing Code
Question No: 25 ( Marks: 1 ) - Please choose one
Above is the circuit diagram of _______.
► Asynchronous up-counter
► Asynchronous down-counter
► Synchronous up-counter
► Synchronous down-counter
Question No: 26 ( Marks: 1 ) ADEEL ABBAS - Please choose one
The sequence of states that are implemented by a n-bit Johnson counter is ► n+2 (n plus 2)
► 2n (n multiplied by 2)
► 2n (2 raise to power n)
► n2 (n raise to power 2)
Question No: 1 ( Marks: 1 ) - Please choose one
NOR Gate can be used to perform the operation of AND, OR and NOT Gate ► FALSE
► TRUE
Question No: 2 ( Marks: 1 ) - Please choose one
The output of an XNOR gate is 1 when ____________I) All the inputs are zero
II) Any of the inputs is zero
III) Any of the inputs is one
IV) All the inputs are one
► I Only
► IV Only
► I and IV only
► II and III only
Question No: 3 ( Marks: 1 ) - Please choose one
NAND gate is formed by connecting _________ ► AND Gate and then NOT Gate
► NOT Gate and then AND Gate
► AND Gate and then OR Gate
► OR Gate and then AND Gate
Question No: 4 ( Marks: 1 ) - Please choose one
Consider A=1,B=0,C=1. A, B and C represent the input of three bit NAND gate the output of the NAND gate will be _____ ► Zero
► One
► Undefined
► No output as input is invalid
Question No: 5 ( Marks: 1 ) - Please choose one
The capability that allows the PLDs to be programmed after they have been installed on a circuit board is called __________ ► Radiation-Erase programming method (REPM)
► In-System Programming (ISP)
► In-chip Programming (ICP)
► Electronically-Erase programming method(EEPM)
Question No: 6 ( Marks: 1 ) - Please choose one
The ABEL symbol for “OR” operation is ► !
► &
► #
► $
Question No: 7 ( Marks: 1 ) - Please choose one
If S=1 and R=1, then Q(t+1) = _________ for negative edge triggered flip-flop ► 0
► 1
► Invalid
► Input is invalid
Question No: 8 ( Marks: 1 ) - Please choose one
The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________ ► Doesn’t have an invalid state
► Sets to clear when both J = 0 and K = 0
► It does not show transition on change in pulse
► It does not accept asynchronous inputs
Question No: 9 ( Marks: 1 ) - Please choose one
For a gated D-Latch if EN=1 and D=1 then Q(t+1) = _________ ► 0
► 1
► Q(t)
► Invalid
Question No: 10 ( Marks: 1 ) - Please choose one
In asynchronous digital systems all the circuits change their state with respect to a common clock ► True
► False
Question No: 11 ( Marks: 1 ) - Please choose one
A positive edge-triggered flip-flop changes its state when ________________ ► Low-to-high transition of clock
► High-to-low transition of clock
► Enable input (EN) is set
► Preset input (PRE) is set
Question No: 12 ( Marks: 1 ) - Please choose one
___________ is one of the examples of asynchronous inputs. ► J-K input
► S-R input
► D input
► Clear Input (CLR)
Question No: 13 ( Marks: 1 ) - Please choose one
The _____________ input overrides the ________ input ► Asynchronous, synchronous
► Synchronous, asynchronous
► Preset input (PRE), Clear input (CLR)
► Clear input (CLR), Preset input (PRE)
Question No: 14 ( Marks: 1 ) - Please choose one
Following Is the circuit diagram of mono-stable device which gate will be replaced by the red colored rectangle in the circuit.
► AND
► NAND
► NOR
► XNOR
Question No: 15 ( Marks: 1 ) - Please choose one
In ________ outputs depend only on the combination of current state and inputs. ► Mealy machine
► Moore
► State Reduction table
► State Assignment table
Question No: 16 ( Marks: 1 ) - Please choose one
________ is used to simplify the circuit that determines the next state. ► State diagram
► Next state table
► State reduction
► State assignment
Question No: 17 ( Marks: 1 ) - Please choose one
A multiplexer with a register circuit converts _________ ► Serial data to parallel
► Parallel data to serial
► Serial data to serial
► Parallel data to parallel
Question No: 18 ( Marks: 1 ) - Please choose one
In asynchronous transmission when the transmission line is idle, _________ ► It is set to logic low
► It is set to logic high
► Remains in previous state
► State of transmission line is not used to start transmission
Question No: 19 ( Marks: 1 ) - Please choose one
In the following statement Z PIN 20 ISTYPE ‘reg.invert’;
The keyword “reg.invert” indicates ________
► An inverted register input
► An inverted register input at pin 20
► Active-high Registered Mode output
► Active-low Registered Mode output
Question No: 20 ( Marks: 1 ) - Please choose one
A Nibble consists of _____ bits ► 2
► 4
► 8
► 16
Question No: 21 ( Marks: 1 ) - Please choose one
The output of this circuit is always ________. ► 1
► 0
► A
►
Question No: 22 ( Marks: 1 ) - Please choose one
At T0 the value stored in a 4-bit left shift was “1”. What will be the value of register after three clock pulses? ► 2
► 4
► 6
► 8
Question No: 23 ( Marks: 1 ) - Please choose one
A bidirectional 4-bit shift register is storing the nibble 1110. Its 
input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing ________. ► 1110
► 0111
► 1000
► 1001
Question No: 24 ( Marks: 1 ) - Please choose one
The high density FLASH memory cell is implemented using ______________ ► 1 floating-gate MOS transistor
► 2 floating-gate MOS transistors
► 4 floating-gate MOS transistors
► 6 floating-gate MOS transistors
Question No: 25 ( Marks: 1 ) - Please choose one
In order to synchronize two devices that consume and produce data at different rates, we can use _________ ► Read Only Memory
► Fist In First Out Memory
► Flash Memory
► Fast Page Access Mode Memory
Question No: 26 ( Marks: 1 ) - Please choose one
If the FIFO Memory output is already filled with data then ________ ► It is locked; no data is allowed to enter
► It is not locked; the new data overwrites the previous data.
► Previous data is swapped out of memory and new data enters
► None of given options
Question No: 27 ( Marks: 1 ) - Please choose one
The process of converting the analogue signal into a digital representation (code) is known as ___________ ► Strobing
► Amplification
► Quantization
► Digitization
Question No: 28 ( Marks: 1 ) - Please choose one
Above is the circuit diagram of _______.
► Asynchronous up-counter
► Asynchronous down-counter
► Synchronous up-counter
► Synchronous down-counter
Question No: 29 ( Marks: 1 ) - Please choose one
is an example of ______________ ► Product of sum form
► Sum of product form
► Demorgans law
► Associative law
Question No: 30 ( Marks: 1 ) - Please choose one
Q2 :=Q1 OR X OR Q3The above ABEL expression will be
► Q2:= Q1 $ X $ Q3
► Q2:= Q1 # X # Q3
► Q2:= Q1 & X & Q3
► Q2:= Q1 ! X ! Q3
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