FINALTERM EXAMINATION
Fall 2009
CS302- Digital Logic Design (Session - 4)
Time: 120 min
Marks: 75
Question No: 1 ( Marks: 1 ) - Please choose one
NOR Gate can be used to perform the operation of AND, OR and NOT Gate ► FALSE
► TRUE
Question No: 2 ( Marks: 1 ) - Please choose one
The output of an XNOR gate is 1 when ____________I) All the inputs are zero
II) Any of the inputs is zero
III) Any of the inputs is one
IV) All the inputs are one
► I Only
► IV Only
► I and IV only
► II and III only
Question No: 3 ( Marks: 1 ) - Please choose one
NAND gate is formed by connecting _________ ► AND Gate and then NOT Gate
► NOT Gate and then AND Gate
► AND Gate and then OR Gate
► OR Gate and then AND Gate
Question No: 4 ( Marks: 1 ) - Please choose one
Consider A=1,B=0,C=1. A, B and C represent the input of three bit NAND gate the output of the NAND gate will be _____ ► Zero
► One
► Undefined
► No output as input is invalid
Question No: 5 ( Marks: 1 ) - Please choose one
The capability that allows the PLDs to be programmed after they have been installed on a circuit board is called __________ ► Radiation-Erase programming method (REPM)
► In-System Programming (ISP)
► In-chip Programming (ICP)
► Electronically-Erase programming method(EEPM)
Question No: 6 ( Marks: 1 ) - Please choose one
The ABEL symbol for “OR” operation is ► !
► &
► #
► $
Question No: 7 ( Marks: 1 ) - Please choose one
If S=1 and R=1, then Q(t+1) = _________ for negative edge triggered flip-flop ► 0
► 1
► Invalid
► Input is invalid
Question No: 8 ( Marks: 1 ) - Please choose one
The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________ ► Doesn’t have an invalid state
► Sets to clear when both J = 0 and K = 0
► It does not show transition on change in pulse
► It does not accept asynchronous inputs
Question No: 9 ( Marks: 1 ) - Please choose one
For a gated D-Latch if EN=1 and D=1 then Q(t+1) = _________ ► 0
► 1
► Q(t)
► Invalid
Question No: 10 ( Marks: 1 ) - Please choose one
In asynchronous digital systems all the circuits change their state with respect to a common clock ► True
► False
Question No: 11 ( Marks: 1 ) - Please choose one
A positive edge-triggered flip-flop changes its state when ________________ ► Low-to-high transition of clock
► High-to-low transition of clock
► Enable input (EN) is set
► Preset input (PRE) is set
Question No: 12 ( Marks: 1 ) - Please choose one
___________ is one of the examples of asynchronous inputs. ► J-K input
► S-R input
► D input
► Clear Input (CLR)
Question No: 13 ( Marks: 1 ) - Please choose one
The _____________ input overrides the ________ input ► Asynchronous, synchronous
► Synchronous, asynchronous
► Preset input (PRE), Clear input (CLR)
► Clear input (CLR), Preset input (PRE)
Question No: 14 ( Marks: 1 ) - Please choose one
Following Is the circuit diagram of mono-stable device which gate will be replaced by the red colored rectangle in the circuit.
► AND
► NAND
► NOR
► XNOR
Question No: 15 ( Marks: 1 ) - Please choose one
In ________ outputs depend only on the combination of current state and inputs. ► Mealy machine
► Moore
► State Reduction table
► State Assignment table
Question No: 16 ( Marks: 1 ) - Please choose one
________ is used to simplify the circuit that determines the next state. ► State diagram
► Next state table
► State reduction
► State assignment
Question No: 17 ( Marks: 1 ) - Please choose one
A multiplexer with a register circuit converts _________ ► Serial data to parallel
► Parallel data to serial
► Serial data to serial
► Parallel data to parallel
Question No: 18 ( Marks: 1 ) - Please choose one
In asynchronous transmission when the transmission line is idle, _________ ► It is set to logic low
► It is set to logic high
► Remains in previous state
► State of transmission line is not used to start transmission
Question No: 19 ( Marks: 1 ) - Please choose one
In the following statement Z PIN 20 ISTYPE ‘reg.invert’;
The keyword “reg.invert” indicates ________
► An inverted register input
► An inverted register input at pin 20
► Active-high Registered Mode output
► Active-low Registered Mode output
Question No: 20 ( Marks: 1 ) - Please choose one
A Nibble consists of _____ bits ► 2
► 4
► 8
► 16
Question No: 21 ( Marks: 1 ) - Please choose one
The output of this circuit is always ________. 
► 1
► 0
► A
► 
Question No: 22 ( Marks: 1 ) - Please choose one
At T0 the value stored in a 4-bit left shift was “1”. What will be the value of register after three clock pulses? ► 2
► 4
► 6
► 8
Question No: 23 ( Marks: 1 ) - Please choose one
A bidirectional 4-bit shift register is storing the nibble 1110. Its 
input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing ________. ► 1110
► 0111
► 1000
► 1001
Question No: 24 ( Marks: 1 ) - Please choose one
The high density FLASH memory cell is implemented using ______________ ► 1 floating-gate MOS transistor
► 2 floating-gate MOS transistors
► 4 floating-gate MOS transistors
► 6 floating-gate MOS transistors
Question No: 25 ( Marks: 1 ) - Please choose one
In order to synchronize two devices that consume and produce data at different rates, we can use _________ ► Read Only Memory
► Fist In First Out Memory
► Flash Memory
► Fast Page Access Mode Memory
Question No: 26 ( Marks: 1 ) - Please choose one
If the FIFO Memory output is already filled with data then ________ ► It is locked; no data is allowed to enter
► It is not locked; the new data overwrites the previous data.
► Previous data is swapped out of memory and new data enters
► None of given options
Question No: 27 ( Marks: 1 ) - Please choose one
The process of converting the analogue signal into a digital representation (code) is known as ___________ ► Strobing
► Amplification
► Quantization
► Digitization
Question No: 28 ( Marks: 1 ) - Please choose one
Above is the circuit diagram of _______.
► Asynchronous up-counter
► Asynchronous down-counter
► Synchronous up-counter
► Synchronous down-counter
Question No: 29 ( Marks: 1 ) - Please choose one
is an example of ______________ ► Product of sum form
► Sum of product form
► Demorgans law
► Associative law
Question No: 30 ( Marks: 1 ) - Please choose one
Q2 :=Q1 OR X OR Q3The above ABEL expression will be
► Q2:= Q1 $ X $ Q3
► Q2:= Q1 # X # Q3
► Q2:= Q1 & X & Q3
► Q2:= Q1 ! X ! Q3
Question No: 31 ( Marks: 1 )
How the “hour counter” is implemented in a digital clock (i.e. how many counters are used and what is their configuration Mod)?Question No: 32 ( Marks: 1 )
The top of the stack contains the value “5” and bottom of the stack contains the value “6”, a pop (read data from stack) operation was executed, which value would be read?Question No: 33 ( Marks: 2 )
What kind of devices use the shift register based First In First Out (FIFO) memory?Ans:
FIFOs are used commonly in electronic circuits for buffering and flow control which is from hardware to software. In hardware form a FIFO primarily consists of a set of read and write pointers, storage and control logic. Storage may be SRAM, flip-flops, latches or any other suitable form of storage. For FIFOs of non-trivial size a dual-port SRAM is usually used where one port is used for writing and the other is used for reading.
Question No: 34 ( Marks: 2 )
Differentiate between positive-edge triggered flip-flop and negative edge-triggered flip-flop.Ans:
A negative edge triggered flip-flop generates an output pulse in response to a negative edge of a clock signal. A first set of nodes receives data input signals, and a second set of nodes receives select input signals for selecting one data input signal as a selected data input signal. The clock node receives the clock signal which has a positive edge and a negative edge. A header circuit connects to the second set of nodes and to the clock node, and integrates the clock signal with the select input signals to generate at least one control signal. A pulse generator circuit connects to the first set of nodes, the header circuit and the output node. The pulse generator circuit generates an output pulse on the output node in response to a control signal and the selected data input signal.
The operation and truth table for a negative edge-triggered flip-flop are the same as those for a positive except that the falling edge of the clock pulse is the triggering edge.
Question No: 35 ( Marks: 3 )
Name some of the important operating characteristics of flip-flops Ans;
The operating characteristics mention here apply to all flip-flops regardless of the particular form of the circuit. They are typically found in data sheets for integrated circuits. They specify the performance, operating requirements, and operating limitations of the circuit.
Propagation Delay Time - is the interval of time required after an input signal has been applied for the resulting output change to occur.
Propagation Delay Time - is the interval of time required after an input signal has been applied for the resulting output change to occur.
Set-Up Time - is the minimum interval required for the logic levels to be maintained constantly on the inputs (J and K, or S and R, or D) prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop.
Hold Time - is the minimum interval required for the logic levels to remain on the inputs after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop.
Maximum Clock Frequency - is the highest rate that a flip-flop can be reliably triggered.
Power Dissipation - is the total power consumption of the device.
Pulse Widths - are the minimum pulse widths specified by the manufacturer for the Clock, SET and CLEAR inputs.
Question No: 36 ( Marks: 3 )
What is memory expansion process? Computers ad digital system have the capability to to allow RAM memory to be extended as the needed arise by inserting extra memory in dedicated memory sockets on the computer motherboard…….th e total amount of memory that is supported by any digital system depends upon the size of the address bus of micro processor or a micro controller.
Question No: 37 ( Marks: 3 )
Write down at least three characteristics of serial in / serial out 4-bit right shift register. Ans:
A serial-in/serial-out shift register has a clock input, a data input, and a data output from the last stage. In general, the other stage outputs are not available Otherwise, it would be a serial-in, parallel-out shift register.. The waveforms below are applicable to either one of the preceding two versions of the serial-in, serial-out shift register. The three pairs of arrows show that a three stage shift register temporarily stores 3-bits of data and delays it by three clock periods from input to output.
Question No: 38 ( Marks: 5 )
Explain Flash Analogue-to Digital Converter.Flash Analogue-to Digital Converter:
A flash analogue to digital converter is the fastest type of converter we use. Like the successive approximation converter it works by comparing the input signal to a reference voltage, but a flash converter has as many comparators as there are steps in the comparison. An 8-bit converter, therefore, has 2 to the power 8, or 256, comparators.
The resistor net and comparators provide an input to the combinational logic circuit, so the conversion time is just the propagation delay through the network - it is not limited by the clock rate or some convergence sequence. It is the fastest type of ADC available, but requires a comparator for each value of output (63 for 6-bit, 255 for 8-bit, etc.) Such ADCs are available in IC form up to 8-bit and 10-bit flash ADCs (1023 comparators) are planned. The encoder logic executes a truth table to convert the ladder of inputs to the binary number output.
Question No: 39 ( Marks: 5 )
Explain the next-state table with the help of a table for any sequential circuit. Ans
The state table representation of a sequential circuit consists of three sections labelled present state, next state and output. The present state designates the state of flip-flops before the occurrence of a clock pulse. The next state shows the states of flip-flops after the clock pulse, and the output section lists the value of the output variables during the present state.
| Present state Q1Q2 | Next state x=0 | Next state x=1 | Out put x=0 | Out put x=1 |
| 00 | 11 | 01 | 0 | 0 |
| 01 | 11 | 00 | 0 | 0 |
| 10 | 10 | 11 | 0 | 1 |
| 11 | 10 | 10 | 0 | 1 |
| | | | | |
Question No: 40 ( Marks: 10 )
Why the inputs of S-R, J-K and D-flip-flops are called synchronous inputs. What are asynchronous inputs, explain effect of “PRE” and “CLR” inputs on flip-flops.Ans:
The normal data inputs to a flip flop (D, S and R, or J and K) are referred to as synchronous inputs because they have effect on the outputs (Q and not-Q) only in step, or in sync, with the clock signal transitions. These extra inputs that I now bring to your attention are called asynchronous because they can set or reset the flip-flop regardless of the status of the clock signal. Typically, they're called preset and clear: When the preset input is activated, the flip-flop will be set (Q=1, not-Q=0) regardless of any of the synchronous inputs or the clock. When the clear input is activated, the flip-flop will be reset (Q=0, not-Q=1), regardless of any of the synchronous inputs or the clock. So, what happens if both preset and clear inputs are activated? Surprise, surprise: we get an invalid state on the output, where Q and not-Q go to the same state, the same as our old friend, the S-R latch! Preset and clear inputs find use when multiple flip-flops are ganged together to perform a function on a multi-bit binary word, and a single line is needed to set or reset them all at once.
Asynchronous inputs, just like synchronous inputs, can be engineered to be active-high or active-low. If they're active-low, there will be an inverting bubble at that input lead on the block symbol, just like the negative edge-trigger clock inputs.
Sometimes the designations "PRE" and "CLR" will be shown with inversion bars above thvem, to further denote the negative logic of these inputs:
Question No: 41 ( Marks: 10 )
Explain the following in context of Memory:Address signals
A memory circuit, in using address transition detection to equilibrate bit lines, generates a summation address transition signal for the row address as well as a summation address transition signal for the column address. There is a transition detector for each address signal. The outputs of the transition detectors for the row address signals are summed in at least two logic stages using CMOS logic gates to generate the summation address signal for the row address. Similarly, the outputs of the transition detectors for the column address signals are summed in at least two logic stages using CMOS logic gates to generate the summation address signal for the column address.
Data signals
Method of how information is transferred; usually it is transferred in binary code in signals or pulses.
A phase lock oscillator includes a phase discriminator that develops an error signal by comparing a clock from a voltage controlled oscillator with incoming random data bits. In the absence of data, the phase lock oscillator is inactive. However, when data is sensed, a logic and delay network in the phase www.allvupastpapers.blogspot.com
discriminator develops an error voltage of suitable polarity and amplitude, indicative of the lead or lag between the data and clock signals. The error voltage is applied to the voltage controlled oscillator to modify the frequency and phase of the clock. Furthermore, first and second integrations are provided by the phase discriminator and an integrator respectively so that the steady state phase error is held close to zero.
It is known that spurious variations in the mechanical or electrical parameters of a storage system cause unwanted displacement and shift of the signal being processed, thus necessitating frequency and phase compensation. To this end, synchronizing systems, servosystems, phase lock oscillator circuits, separation circuits and the like are employed.
By : ADEEL ABBAS
www.allvupastpapers.blogspot.com
AdeelAbbasbk@gmail.com
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