Question No: 1 ( Marks: 1 ) - Please choose one
The output of an AND gate is one when _______ ► All of the inputs are one
► Any of the input is one
► Any of the input is zero
► All the inputs are zero
Question No: 2 ( Marks: 1 ) - Please choose one
The OR Gate performs a Boolean _______ function ► Addition
► Subtraction
► Multiplication
► Division
Question No: 3 ( Marks: 1 ) - Please choose one
A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the resulting output of each value. ► True
► False
Question No: 4 ( Marks: 1 ) - Please choose one
The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels? ► A > B = 1, A < B = 0, A < B = 1
► A > B = 0, A < B = 1, A = B = 0
► A > B = 1, A < B = 0, A = B = 0
► A > B = 0, A < B = 1, A = B = 1
Question No: 5 ( Marks: 1 ) - Please choose one
The diagram above shows the general implementation of _____ form
► boolean
► arbitrary
► POS
► SOP
Question No: 6 ( Marks: 1 ) - Please choose one
The device shown here is most likely a 
► Comparator
► Multiplexer
► Demultiplexer
► Parity generator
Question No: 7 ( Marks: 1 ) - Please choose one
Demultiplexer converts _______ data to __________ data ► Parallel data, serial data
► Serial data, parallel data
► Encoded data, decoded data
► All of the given options.
Question No: 8 ( Marks: 1 ) - Please choose one
Flip flops are also called _____________ ► Bi-stable dualvibrators
► Bi-stable transformer
► Bi-stable multivibrators
► Bi-stable singlevibrators
Question No: 9 ( Marks: 1 ) - Please choose one
If S=1 and R=0, then Q(t+1) = _________ for positive edge triggered flip-flop ► 0
► 1
► Invalid
► Input is invalid
Question No: 10 ( Marks: 1 ) - Please choose one
If S=1 and R=1, then Q(t+1) = _________ for negative edge triggered flip-flop ► 0
► 1
► Invalid
► Input is invalid
Question No: 11 ( Marks: 1 ) - Please choose one
The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________ ► Doesn’t have an invalid state
► Sets to clear when both J = 0 and K = 0
► It does not show transition on change in pulse
► It does not accept asynchronous inputs
Question No: 12 ( Marks: 1 ) - Please choose one
The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of the flip-flop. ► Set-up time
► Hold time
► Pulse Interval time
► Pulse Stability time (PST)
Question No: 13 ( Marks: 1 ) - Please choose one
We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by ___________ ► Using S-R Flop-Flop
► D-flipflop
► J-K flip-flop
► T-Flip-Flop
Question No: 14 ( Marks: 1 ) - Please choose one
In asynchronous digital systems all the circuits change their state with respect to a common clock ► True
► False
Question No: 15 ( Marks: 1 ) - Please choose one
A positive edge-triggered flip-flop changes its state when ________________ ► Low-to-high transition of clock
► High-to-low transition of clock
► Enable input (EN) is set
► Preset input (PRE) is set
Question No: 16 ( Marks: 1 ) - Please choose one
A negative edge-triggered flip-flop changes its state when ________________ ► Enable input (EN) is set
► Preset input (PRE) is set
► Low-to-high transition of clock
► High-to-low transition of clock
Question No: 17 ( Marks: 1 ) - Please choose one
A flip-flop is connected to +5 volts and it draws 5 mA of current during its operation, the power dissipation of the flip-flop is ► 10 mW
► 25 mW
► 64 mW
► 1024
Question No: 18 ( Marks: 1 ) - Please choose one
__________occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. ► Race condition
► Clock Skew
► Ripple Effect
► None of given options
Question No: 19 ( Marks: 1 ) - Please choose one
A counter is implemented using three (3) flip-flops, possibly it will have ________ maximum output status. ► 3
► 7
► 8
► 15
Question No: 20 ( Marks: 1 ) - Please choose one
A divide-by-50 counter divides the input ______ signal to a 1 Hz signal. ► 10 Hz
► 50 Hz
► 100 Hz
► 500 Hz
Question No: 21 ( Marks: 1 ) - Please choose one
The design and implementation of synchronous counters start from _________ ► Truth table
► k-map
► state table
► state diagram
Question No: 22 ( Marks: 1 ) - Please choose one
A synchronous decade counter will have _______ flip-flops ► 3
► 4
► 7
► 10
Question No: 23 ( Marks: 1 ) - Please choose one
The output of this circuit is always ________. 
► 1
► 0
► A
► 
Question No: 24 ( Marks: 1 ) - Please choose one
At T0 the value stored in a 4-bit left shift was “1”. What will be the value of register after three clock pulses? ► 2
► 4
► 6
► 8
Question No: 25 ( Marks: 1 ) - Please choose one
In _______ the 
output of the last flip-flop of the shift register is connected to the data input of the first flip-flop. ► Moore
► Meally machine
► Johnson counter
► Ring counter
Question No: 26 ( Marks: 1 ) - Please choose one
In ________ Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop of the shift register. ► Moore
► Meally machine
► Johnson counter
► Ring counter
Question No: 27 ( Marks: 1 ) - Please choose one
Which is not characteristic of a shift register? ► Serial in/parallel in
► Serial in/parallel out
► Parallel in/serial out
► Parallel in/parallel out
Question No: 28 ( Marks: 1 ) - Please choose one
Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.) ► 1100
► 0011
► 0000
► 1111
Question No: 29 ( Marks: 1 ) - Please choose one
The _________ of a ROM is the time it takes for the data to appear at the DataOutput of the ROM chip after an address is applied at the address input lines
► Write Time
► Recycle Time
► Refresh Time
► Access Time
Question No: 30 ( Marks: 1 ) - Please choose one
The sequence of states that are implemented by a n-bit Johnson counter is ► n+2 (n plus 2)
► 2n (n multiplied by 2)
► 2n (2 raise to power n)
► n2 (n raise to power 2)
Question No: 1 ( Marks: 1 ) - Please choose one
The maximum number that can be represented using unsigned octal system is _______ ► 1
► 7
► 9
► 16
Question No: 2 ( Marks: 1 ) - Please choose one
If we add “723” and “134” by representing them in floating point notation i.e. by first, converting them in floating point representation and then adding them, the value of exponent of result will be ________ ► 0
► 1
► 2
► 3
Question No: 3 ( Marks: 1 ) - Please choose one
The diagram given below represents __________
► Demorgans law
► Associative law
► Product of sum form
► Sum of product form
Question No: 4 ( Marks: 1 ) - Please choose one
The range of Excess-8 code is from ______ to ______ ► +7 to -8
► +8 to -7
► +9 to -8
► -9 to +8
Question No: 5 ( Marks: 1 ) - Please choose one
A non-standard POS is converted into a standard POS by using the rule _____ ► 
► 
► 
► A+B = B+A
Question No: 6 ( Marks: 1 ) - Please choose one
The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms ► 4
► 8
► 12
► 16
Question No: 7 ( Marks: 1 ) - Please choose one
The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels? ► A > B = 1, A < B = 0, A < B = 1
► A > B = 0, A < B = 1, A = B = 0
► A > B = 1, A < B = 0, A = B = 0
► A > B = 0, A < B = 1, A = B = 1
Question No: 8 ( Marks: 1 ) - Please choose one
A particular Full Adder has ► 3 inputs and 2 output
► 3 inputs and 3 output
► 2 inputs and 3 output
► 2 inputs and 2 output
Question No: 9 ( Marks: 1 ) - Please choose one
The function to be performed by the processor is selected by set of inputs known as ________ ► Function Select Inputs
► MicroOperation selectors
► OPCODE Selectors
► None of given option
Question No: 10 ( Marks: 1 ) - Please choose one
For a 3-to-8 decoder how many 2-to-4 decoders will be required? ► 2
► 1
► 3
► 4
Question No: 11 ( Marks: 1 ) - Please choose one
GAL is an acronym for ________. ► Giant Array Logic
► General Array Logic
► Generic Array Logic
► Generic Analysis Logic
Question No: 12 ( Marks: 1 ) - Please choose one
The Quad Multiplexer has _____ outputs ► 4
► 8
► 12
► 16
Question No: 13 ( Marks: 1 ) - Please choose one
A.(B.C) = (A.B).C is an expression of __________ ► Demorgan’s Law
► Distributive Law
► Commutative Law
► Associative Law
Question No: 14 ( Marks: 1 ) - Please choose one
2's complement of any binary number can be calculated by ► adding 1's complement twice
► adding 1 to 1's complement
► subtracting 1 from 1's complement.
► calculating 1's complement and inverting Most significant bit
Question No: 15 ( Marks: 1 ) - Please choose one
The binary value “1010110” is equivalent to decimal __________ ► 86
► 87
► 88
► 89
Question No: 16 ( Marks: 1 ) - Please choose one
Tri-State Buffer is basically a/an _________ gate. ► AND
► OR
► NOT
► XOR
The diagram given below represents __________
► Demorgans law
► Associative law
► Product of sum form
► Sum of product form
Question No: 2 ( Marks: 1 ) - Please choose one
Excess-8 code assigns _______ to “+7” ► 0000
► 1001
► 1000
► 1111
Question No: 3 ( Marks: 1 ) - Please choose one
NOR gate is formed by connecting _________ ► OR Gate and then NOT Gate
► NOT Gate and then OR Gate
► AND Gate and then OR Gate
► OR Gate and then AND Gate
Question No: 4 ( Marks: 1 ) - Please choose one
A full-adder has a Cin = 0. What are the sum (<PRIVATE "TYPE=PICT;ALT=sigma">
) and the carry (Cout) when A = 1 and B = 1?| ► |
= 0, Cout = 0= 0, Cout = 0 ► = 0, Cout = 1
= 0, Cout = 1 ► = 1, Cout = 0
= 1, Cout = 0 ► = 1, Cout = 1
= 1, Cout = 1Question No: 5 ( Marks: 1 ) - Please choose one
A particular half-adder has ► 2 inputs and 1 output
► 2 inputs and 2 output
► 3 inputs and 1 output
► 3 inputs and 2 output
Question No: 6 ( Marks: 1 ) - Please choose one
The four outputs of two 4-input multiplexers, connected to form a 16-input multiplexer, are connected together through a 4-input __________ gate ► AND
► OR
► NAND
► XOR
Question No: 7 ( Marks: 1 ) - Please choose one
A Field-Programmable Logic Array can be programmed by the user and not by the manufacturer. ► True
► False
Question No: 8 ( Marks: 1 ) - Please choose one
Flip flops are also called _____________ ► Bi-stable dualvibrators
► Bi-stable transformer
► Bi-stable multivibrators
► Bi-stable singlevibrators
Question No: 9 ( Marks: 1 ) - Please choose one
A positive edge-triggered flip-flop changes its state when ________________ ► Low-to-high transition of clock
► High-to-low transition of clock
► Enable input (EN) is set
► Preset input (PRE) is set
Question No: 10 ( Marks: 1 ) - Please choose one
___________ is one of the examples of synchronous inputs. ► J-K input
► EN input
► Preset input (PRE)
► Clear Input (CLR)
Question No: 11 ( Marks: 1 ) - Please choose one
The glitches due to race condition can be avoided by using a ___________ ► Gated flip-flops
► Pulse triggered flip-flops
► Positive-Edge triggered flip-flops
► Negative-Edge triggered flip-flops
Question No: 12 ( Marks: 1 ) - Please choose one
The design and implementation of synchronous counters start from _________ ► Truth table
► k-map
► state table
► state diagram
Question No: 13 ( Marks: 1 ) - Please choose one
The hours counter is implemented using __________ ► Only a single Mod-12 counter is required
► Mod-10 and Mod-6 counters
► Mod-10 and Mod-2 counters
► a single decade counter and a flip-flop
Question No: 14 ( Marks: 1 ) - Please choose one
Given the state diagram of an up/down counter, we can find __________ ► The next state of a present state
► The previous state of a present state
► Both the next and previous states of a given state
► The state diagram shows only the inputs/outputs of a given states
Question No: 15 ( Marks: 1 ) - Please choose one
In ________ outputs depend only on the current state. ► Mealy machine
► Moore
► State Reduction table
► State Assignment table
Question No: 16 ( Marks: 1 ) - Please choose one
A synchronous decade counter will have _______ flip-flops ► 3
► 4
► 7
► 10
Question No: 17 ( Marks: 1 ) - Please choose one
A multiplexer with a register circuit converts _________ ► Serial data to parallel
► Parallel data to serial
► Serial data to serial
► Parallel data to parallel
Question No: 18 ( Marks: 1 ) - Please choose one
The alternate solution for a multiplexer and a register circuit is _________ ► Parallel in / Serial out shift register
► Serial in / Parallel out shift register
► Parallel in / Parallel out shift register
► Serial in / Serial Out shift register
Question No: 19 ( Marks: 1 ) - Please choose one
At T0 the value stored in a 4-bit left shift was “1”. What will be the value of register after three clock pulses? ► 2
► 4
► 6
► 8
Question No: 20 ( Marks: 1 ) - Please choose one
A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register. ► 1
► 2
► 4
► 8
Question No: 21 ( Marks: 1 ) - Please choose one
5-bit Johnson counter sequences through ____ states ► 7
► 10
► 32
► 25
Question No: 22 ( Marks: 1 ) - Please choose one
In ________ Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop of the shift register. ► Moore
► Meally machine
► Johnson counter
► Ring counter
Question No: 23 ( Marks: 1 ) - Please choose one
DRAM stands for __________ ► Dynamic RAM
► Data RAM
► Demoduler RAM
► None of given options
Question No: 24 ( Marks: 1 ) - Please choose one
If the FIFO Memory output is already filled with data then ________ ► It is locked; no data is allowed to enter
► It is not locked; the new data overwrites the previous data.
► Previous data is swapped out of memory and new data enters
► None of given options
Question No: 25 ( Marks: 1 ) - Please choose one
LUT is acronym for _________ ► Look Up Table
► Local User Terminal
► Least Upper Time Period
► None of given options
Question No: 26 ( Marks: 1 ) - Please choose one
______ of a D/A converter is determined by comparing the actual output of a D/A converter with the expected output. ► Resolution
► Accuracy
► Quantization
► Missing Code
Question No: 27 ( Marks: 1 ) - Please choose one
In the circuit diagram of 3-bit synchronous countershown above, The red rectangle would be replaced which gate?
► AND
► OR
► NAND
► XNOR
Question No: 28 ( Marks: 1 ) - Please choose one
When both the inputs of edge-triggered J-K flop-flop are set to logic zero _________ ► The flop-flop is triggered
► Q=0 and Q’=1
► Q=1 and Q’=0
► The output of flip-flop remains unchanged
Question No: 29 ( Marks: 1 ) - Please choose one
A frequency counter ______________ ► Counts pulse width
► Counts no. of clock pulses in 1 second
► Counts high and low range of given clock pulse
► None of given options
By : ADEEL ABBAS
www.allvupastpapers.blogspot.com
AdeelAbbasbk@gmail.com
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