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2) For NOR based SR latch, what will be the output for following conditions if initial output is 1 (5 marks)

a. S=0, R=0

b. S=1, R=0

c. S=0, R=1

d. S=1,R=0

e. S=0,R=0

f. S=1,R=0

Q2

 How combinational circuit are implemented by NAND gates(2

2. Analyze the following truth table and identify combinational logic circuit depicted by this truth table. Also derive the simplified SOP Boolen Expression for this circuit? (5 Marks

the odd parity detector was given

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