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Friday, December 24, 2010

CS302- Digital Logic Design Complete Solved Finalterm Past paper 2010

FINALTERM  EXAMINATION
Spring 2010
CS302- Digital Logic Design (Session - 4)
Time: 90 min
Marks: 58
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Question No: 1    ( Marks: 1 )    - Please choose one
 The ANSI/IEEE Standard 754 defines a __________Single-Precision Floating Point format for binary numbers.

       ► 8-bit
       ► 16-bit
       ► 32-bit
       ► 64-bit
   
Question No: 2    ( Marks: 1 )    - Please choose one
 The decimal “17” in BCD will be represented as _________

       ► 11101
       ► 11011
       ► 10111
       ► 11110
   
Question No: 3    ( Marks: 1 )    - Please choose one
 The basic building block for a logical circuit is _______

       ► A Flip-Flop
       ► A Logical Gate
       ► An Adder
       ► None of given options
   
Question No: 4    ( Marks: 1 )    - Please choose one
 The output of the expression F=A.B.C will be Logic ________ when A=1, B=0, C=1.
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       ► Undefined
       ► One
       ► Zero
       ► No Output as input is invalid.
   
Question No: 5    ( Marks: 1 )    - Please choose one
 ________ is invalid number of cells in a single group formed by the adjacent cells in K-map


       ► 2
       ► 8
       ► 12
       ► 16
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Question No: 6    ( Marks: 1 )    - Please choose one
 The PROM consists of a fixed non-programmable ____________ Gate array configured as a decoder.


       ► AND
       ► OR
       ► NOT
       ► XOR
   
Question No: 7    ( Marks: 1 )    - Please choose one
 ___________ is one of the examples of synchronous inputs.
       ► J-K input
       ► EN input
       ► Preset input (PRE)
       ► Clear Input (CLR)
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Question No: 8    ( Marks: 1 )    - Please choose one
 ___________ is one of the examples of asynchronous inputs.
       ► J-K input
       ► S-R input
       ► D input
       ► Clear Input (CLR)
   
Question No: 9    ( Marks: 1 )    - Please choose one
 The _____________ input overrides the ________ input
       ► Asynchronous, synchronous
       ► Synchronous, asynchronous
       ► Preset input (PRE), Clear input (CLR)
       ► Clear input (CLR), Preset input (PRE)
   
Question No: 10    ( Marks: 1 )    - Please choose one
 __________occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay.
       ► Race condition
       ► Clock Skew
       ► Ripple Effect
       ► None of given options
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Question No: 11    ( Marks: 1 )    - Please choose one
 Consider an up/down counter that counts between 0 and 15, if external input(X) is “0” the counter counts upward (0000 to 1111) and if external input (X) is “1” the counter counts downward (1111 to 0000), now suppose that the present state is “1100” and X=1, the next state of the counter will be ___________



       ► 0000
       ► 1101
       ► 1011
       ► 1111
   
Question No: 12    ( Marks: 1 )    - Please choose one
 In a state diagram, the transition from a current state to the next state is determined by

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       ► Current state and the inputs
       ► Current state and outputs
       ► Previous state and inputs
       ► Previous state and outputs
   
Question No: 13    ( Marks: 1 )    - Please choose one
 ________ is used to minimize the possible no. of states of a circuit.

       ► State assignment
       ► State reduction
       ► Next state table
       ► State diagram
   
Question No: 14    ( Marks: 1 )    - Please choose one
 ________ is used to simplify the circuit that determines the next state.
       ► State diagram
       ► Next state table
       ► State reduction
       ► State assignment
   
Question No: 15    ( Marks: 1 )    - Please choose one
 The best state assignment tends to ___________.
       ► Maximizes the number of state variables that don’t change in a group of related states
       ► Minimizes the number of state variables that don’t change in a group of related states
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     ► Minimize the equivalent states
       ► None of given options
   
Question No: 16    ( Marks: 1 )    - Please choose one
 The output of this circuit is always ________.
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       ► 1
       ► 0
       ► A
       ►
   
Question No: 17    ( Marks: 1 )    - Please choose one
 A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register.
       ► 1
       ► 2
       ► 4
       ► 8
   
Question No: 18    ( Marks: 1 )    - Please choose one
 5-bit Johnson counter sequences through ____ states
       ► 7
       ► 10
       ► 32
       ► 25
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Question No: 19    ( Marks: 1 )    - Please choose one
 Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)







       ► 1100
       ► 0011
       ► 0000
       ► 1111
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Question No: 20    ( Marks: 1 )    - Please choose one
 The address from which the data is read, is provided by _______


       ► Depends on circuitry
       ► None of given options
       ► RAM
       ► Microprocessor
   
Question No: 21    ( Marks: 1 )    - Please choose one
 FIFO is an acronym for  __________
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       ► First In, First Out
       ► Fly in, Fly Out
       ► Fast in, Fast Out
       ► None of given options
   
Question No: 22    ( Marks: 1 )    - Please choose one
 LUT is acronym for _________


       ► Look Up Table
       ► Local User Terminal
       ► Least Upper Time Period
       ► None of given options
   
Question No: 23    ( Marks: 1 )    - Please choose one
 The voltage gain of the Inverting Amplifier is given by the relation ________


       ► Vout / Vin = - Rf / Ri
       ► Vout / Rf = - Vin / Ri
       ► Rf / Vin = - Ri / Vout
       ► Rf / Vin =   Ri / Vout
   
Question No: 24    ( Marks: 1 )    - Please choose one
 ______ of a D/A converter is determined by comparing the actual output of a D/A converter with the expected output.

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       ► Resolution
       ► Accuracy
       ► Quantization
       ► Missing Code
   
Question No: 25    ( Marks: 1 )    - Please choose one
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Above is the circuit diagram of _______.

       ► Asynchronous up-counter
       ► Asynchronous down-counter
       ► Synchronous up-counter
       ► Synchronous down-counter
   
Question No: 26    ( Marks: 1 )    - Please choose one
 The sequence of states that are implemented by a n-bit Johnson counter is

       ► n+2 (n plus 2)
       ► 2n   (n multiplied by 2)
       ► 2n   (2 raise to power n)
       ► n2   (n raise to power 2)
   
Question No: 27    ( Marks: 2 )
 Draw the Truth-Table of NOR based S-R Latch

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input
output
S
R
QT +1
0
0
QT
0
1
0
1
0
1
1
1
INVALID


   
Question No: 28    ( Marks: 2 )

Two state assignments are given in the table below. Identify which state assignment is best and why?


States
State assignment 1
State assignment 2
A
00
00
B
01
01
C
11
10
D
10
11

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Ans:
State assignment 2 is best assignment… it Minimizes the number of state variables that don’t change in a group of related states
.

   
Question No: 29    ( Marks: 2 )
 Write down at least two functions of a register.

Ans:
1.      Registers are operating as a coherent unit to hold and generate data.
2.      registers functions also include configuration and start-up of certain features, especially during initialization, buffer storage e.g. video memory for graphics cards, input/output (I/O) of different kinds,

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Question No: 30    ( Marks: 2 )
 Define quantization process.

Ans:
The process by which we can convert an analogue signal into digital signal (code) is known as quantization process.

   
Question No: 31    ( Marks: 3 )
 How can we calculate the frequency of an unknown signal?

Ans:
The frequency of a particular event is accomplished by counting the number of times that event occurs within a specific time interval, then dividing the count by the length of the time interval.


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Question No: 32    ( Marks: 3 )
 Given the following statement used in PLD programming:
Y PIN 23 ISTYPE ‘com’;
Explain what does this statement mean?

Ans:
The Y variable is a ‘Combinational’ output available directly from the AND-OR gate array output. The active-low or active-high output of the Registered Mode can also be specified in the declaration statement


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Question No: 33    ( Marks: 3 )
 Explain dynamic RAM in your own words.

Ans:
Dram use latch to store a single bit of information.the main drawback of it id the discharge of capacitor over a period of time.here four gates are used in making a singlelatch. In terms of transistors, 4 to 6 transistors are required to implement a single storage cell. In order to build memories with higher densities, a single transistor is used to store a binary value. A single transistor can not store a binary value however it is used to charge and discharge a capacitor. The capacitor can not retain the charge, therefore it has to be periodically charged
through a refresh cycle.
   
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Question No: 34    ( Marks: 5 )
 You are given the Next-state table of a moor machine, using this information draw the state diagram of the machine.

Present State
Next State
Q2
Q1
Q0
Q2
Q1
Q0
0
1
1
1
1
1
1
1
1
0
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
0
0
1
1

   
Question No: 35    ( Marks: 5 )
 Explain Memory Select or Enable Signals


Memory Select or Enable Signal:

 There are more than one memory chips to store program
Information in daily use computers. read or write operation is carried out on a single addressable location instantaneously .

The unique location is accessed in one of the several memory chips, so single memory chips is selected before a read or write operation can be carried out. All memory chips have a chip enable or chip select signal which has to be activated before the memory can be accessed.

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Question No: 36    ( Marks: 5 )
 Performance characteristics of D/A converters are determined by five parameters. Name them.


Ans:
Performances characteristics of D/A converters are determined by five parameters are as follow:
  1. Accuracy
  2. Setting time
  3. Monotonicity
  4. Linearity
  5. Resolution

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Posted by aaaa at 11:48 PM

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